In current computer architectures, several levels of memory may be implemented. A hard drive, random access memory (RAM), and cache memory, all represent memory sources that may be used to write and read data. RAM is often used as a computer's main memory. Data consistently being accessed may be read from a hard drive and stored in RAM for faster access. However, RAM is still unable to be accessed in time to meet the high speeds of most new computer processors. While used as the main memory in a computer, RAM accessing may present latency to the computer. A single RAM device can only process a select number of memory requests at one time. Therefore, most processors within an information handling system use cache memory for handling some memory requests. Cache memory is memory local to a processor.
It is possible for a memory client to request to read data from main memory, but receive data from another memory source, such as cache memory. When dealing with memory intensive clients, such as graphics clients, main memory may introduce latencies due to other memory requests, which are pending in a memory controller for processing in main memory. To reduce these latencies encountered when accessing data from main memory, cache memory is used to provide data requested from main memory. Cache memory may store copies of data stored in main memory. However, the cache memory must maintain coherency with the main memory for the data to be valid. Cache coherency is a synchronization of data between cache memory and main memory so that a particular set of data in cache memory is the current version of that data currently stored in main memory.
In order to decrease the response time to requests for information stored in memory, some conventional systems will attempt to fill those requests using information stored in a processor's cache memory. One problem with this scheme, however, is that the data in cache memory does not always represent a current version of the data in main memory. Conventional systems deal with this problem by first determining if cache memory is coherent with main memory; if so the memory controller obtains the data from the cache memory. However, if the cache memory is not coherent with the main memory, then the memory controller fetches the data from main memory.
In the case where the cache memory is not coherent with the main memory, the memory controller must wait until after it has determined that the cache memory is current before it processes the request to fetch the data from main memory, because the memory controller stalls the current memory request and sends a signal to the processor to determine if cache memory is current. While such a method allows data to be accessed from cache memory, it also introduces latency as the memory controller stalls the request to determine the coherency of cache memory. From the above discussion, it is apparent that an improved method for accessing data within a system with multiple memory sources is needed.